Various electronic apparatuses are provided with a power on reset circuit which monitors the rise of a power source voltage and resets a desired circuit when the power source voltage reaches a desired voltage or more. A power on reset circuit generally adopts a system in which a comparator compares a comparison voltage obtained by resistively dividing a power source voltage to a reference voltage. The power on reset circuit adopting this system raises concern that a malfunction may occur when the power source voltage is low.
In order to prevent such a malfunction during the operation at a low power source voltage, it has been devised that a time difference is established between the reference voltage which serves as a reference input of a comparator and the comparison voltage which serves as a comparison input (for example, see Patent Literatures 1 and 2).